A single-wire interface plays an important part in communicating between devices where a complex bus structure is not effective. The lack of effectiveness of a complex bus may be due to either cost or a system constraint, such as area for routing a bus, as may be the case in a vehicle. A single wire bus is able to provide signaling to implement a bidirectional protocol between bus elements and power to a target device.
With reference to FIG. 1A, a single-wire interface 105 couples a master device 110 to a target device 115 in a prior art single-wire-interface system 100. The master device 110 is coupled to an external power supply VDD 120 and ground, and to the single-wire interface 105 via a line 125. The master device 110 may transmit a signal (e.g., data) onto the single-wire interface 105 by driving the line 125.
The target device 115 is coupled to ground and receives both its power and signals from the single-wire interface 105 via a line 130. Within the target device 115, diode 135 is coupled in series with a capacitor 140 between the line 130 and ground. A series connection point 150 at a voltage VCAP, between the diode 135 and a capacitor 140, is coupled to the power input of a target device function 145. Generally, device functions are any type of device intended to be controlled as a target coupled to the single-wire interface 105. The target device function 145 may send a signal (e.g., data) back to the master device 110 via the single-wire interface 105 by driving the line 130 using power stored in the capacitor 140.
With reference to FIG. 1B, during non-communication periods of the single-wire protocol, the single-wire interface signal VBUS is maintained at a specified logic level. For example, the master device 110 may provide a full voltage level from the external power supply 120 to the single-wire interface 105. This allows the capacitors 140 of target devices 115 coupled to the single-wire interface 105 to store charge for powering the target device 115.
During a communications sequence of the single-wire protocol, a first target transaction 170a begins with a first target transaction start time 165. A first capacitor discharge period 175a begins with the first target transaction start time 165 and concludes after the first target transaction 170a by an amount of time necessary for the target 115 to complete logic processing operations relative to that target transaction. Therefore, the first capacitor discharge period 175a is equal to or greater than the first target transaction 170a in length.
After the first capacitor discharge period 175a, a first capacitor recharge period 195a commences at a first bus release time 180a. The first bus release time 180a is determined by the master device 110 and is executed at a time sufficiently long after the conclusion of the first target transaction 170a such that all processing related to transactions on the single-wire interface 105 is concluded by the target device 115. The sufficiency of the period of time to wait for the first bus release time 180a after conclusion of the first capacitor discharge period 175a is determined by one skilled in the art during facilitation of the single-wire protocol with consideration of a literal implementation of the target 115 and the master device 110. For instance, the timing analysis is performed during or after logic design in implementing these bus elements.
The sufficiency of a charging period in general is determined by the longest period of time required to re-establish all charge on the capacitor 140 that has been depleted in a longest capacitor discharge period. For example, a second target transaction 170b in a communication sequence is similar to the first target transaction 170a discussed above. However, the duration of the second target transaction 170b may be different than the duration of the first target transaction 170a. The duration of a second capacitor discharge period 175b will likewise vary according to the duration of the second target transaction 170b. Therefore, a second capacitor recharge period 195b different from the first capacitor recharge period 195a may be required to fully replenish the charge on the capacitor 140.
Even with a longest period of time required for recharging the capacitor 140, there is still a significant drawback in that the recharge voltage level achieved is at one diode forward bias voltage drop 185 below the power supply voltage 190 provided on the single-wire interface 105. In a low voltage system, this amount of voltage drop 185 may mean that the available voltage level remaining to power target device functions may not be sufficient for proper operation of those functions or for the requisite duration. What is needed is a way of selectively providing a full power-supply voltage level 190 from the single-wire interface 105 to the capacitor 140 during periods of non-communication.